SH7760 Datasheet, PDF (221/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

8.3 Exception Flow
8.3.1 Exception Flow
Figure 8.1 shows an outline flowchart of the basic operations in instruction execution and
exception handling. For the sake of clarity, the following description assumes that instructions are
executed sequentially, one by one. Figure 8.1 shows the relative priority order of the different
kinds of exceptions (reset, general exception, and interrupt). Register settings in the event of an
exception are shown only for SSR, SPC, SGR, EXPEVT/INTEVT, SR, and PC. However, other
registers may be set automatically by hardware, depending on the exception. For details, see
section 8.5, Operation. Also, see section 8.5.4, Priority Order with Multiple Exceptions, for
exception handling during execution of a delayed branch instruction and a delay slot instruction,
or in the case of instructions in which two data accesses are performed.
Reset
Yes
requested?
No
Execute next instruction
General
exception requested?
No
Interrupt
requested?
No
Is highest-
Yes
priority exception
Yes
re-exception
type?
Cancel instruction execution
No
result
Yes
SSR ← SR
SPC ← PC
SGR ← R15
EXPEVT/INTEVT ← exception code
SR.{MD,RB,BL} ← 111
PC ← (BRCR.UBDE=1 && User_Break?
DBR: (VBR + Offset))
EXPEVT ← exception code
SR. {MD, RB, BL, FD, IMASK} ← 11101111
PC ← H'A000 0000
Figure 8.1 Instruction Execution and Exception Handling
Rev. 1.0, 02/03, page 171 of 1294