SH7760 Datasheet, PDF (525/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
1
DIV1
0
0
DIV0
1
R/W Frequency Division Ratio Setting
R/W These bits specify the DCK clock frequency
division ratio with respect to the CKIO clock.
00: Setting prohibited
01: CKIO × 1/1
10: CKIO × 1/2
11: CKIO × 1/3
12.4.3 Module Clock Control Register (MCKCR)
MCKCR is a 32-bit readable/writable register that specifies the frequency division ratio of the
module clock (Fck).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
- ^{FLM FLM FLM FLM}
CK3 CK2 CK1 CK0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W
Bit
Bit Name
31 to 4 —
3
FLMCK3
2
FLMCK2
1
FLMCK1
0
FLMCK0
Initial Value R/W
All 0
R
0
R/W
0
R/W
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Module Clock Frequency Division Ratio Setting
These bits specify the Fck clock frequency
division ratio with respect to the peripheral clock.
0000: Peripheral clock × 1/1
0001: Setting prohibited
0010: Setting prohibited
0011: Setting prohibited
Other than above: Setting prohibited
Rev. 1.0, 02/03, page 475 of 1294