SH7760 Datasheet, PDF (319/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit
Name Value R/W Description
15
TRWL2 0
14
TRWL1 0
13
TRWL0 0
R/W Write Precharge Delay
R/W
Specify the synchronous DRAM write precharge delay in
R/W
these bits. In auto-precharge mode, specify the time
after a write cycle before the next bank active command
is issued. After a write cycle, the next active command is
not issued for a period of TPC + TRWL. In RAS down
mode, specify the time after a write cycle before the next
precharge command is issued. After a write cycle, the
next precharge command is not issued for a period of
TRWL. This setting is valid only when synchronous
DRAM interface is in use. For details on these bit
settings and the period in which no command is issued,
refer to section 33.3.3, Bus Timing.
Write Precharge ACT Delay Time
000: 1
001: 2
010: 3*¹
011: 4*¹
100: 5*¹
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
12
TRAS2 0
11
TRAS1 0
10
TRAS0 0
R/W Refresh Period
R/W
When the synchronous DRAM interface is in use, the
R/W
bank active command is not issued for a period of TRC*²
+ TRAS after an auto-refresh command is issued.
Command Issuance Gap after Synchronous
DRAM Refresh
000: 4 + TRC
001: 5 + TRC
010: 6 + TRC
011: 7 + TRC
100: 8 + TRC
101: 9 + TRC
110: 10 + TRC
111: 11 + TRC
Rev. 1.0, 02/03, page 269 of 1294