SH7760 Datasheet, PDF (512/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 11.13 Data Alignment between External Bus and USB Bridge Bus
Transfer Mode
Byte boundary mode
Access Size
Byte
Word/longword
boundary
mode
Longword
Byte
Longword
Address
4n + 0
4n + 1
4n + 2
4n + 3
4n + 0
4n + 0
4n + 1
4n + 2
4n + 3
4n + 0
Peripheral Bus
USB Bridge Bus
31
B0
0 31
0
B0
31
B1
0 31
0
B1
31
0 31
0
B2
B2
31
0 31
0
B3
B3
31
0
B0 B1 B2 B3
31
0
B3 B2 B1 B0
31
B0
0 31
0
B0
31
0 31
0
B1
B1
31
0 31
0
B2
B2
31
0 31
0
B3
B3
31
0
B0 B1 B2 B3
31
0
B2 B3 B0 B1
11.6.14 DMABRG Interrupts
The DMABRG issues three interrupts: a USB address error interrupt, an all data transfer end
interrupt, and a half data transfer end interrupt. The DMABRG generates a USB address error
interrupt request for a DMA transfer request from the USB, an all data transfer end interrupt
request for a DMA transfer request from the HAC, SSI, or USB, and a half data transfer end
interrupt request for a transfer request from the HAC or SSI. A DMABRG interrupt request is not
generated for a DMA transfer request from the LCDC. When a reset is cancelled, the interrupt
priority is in the following order: a USB address error interrupt, an all data transfer end interrupt,
and a half data transfer end interrupt.
Rev. 1.0, 02/03, page 462 of 1294