SH7760 Datasheet, PDF (808/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Control, Timer and CAN Interface. The figure below shows the block diagram of the module. The
bus interface timing is designed based on SH internal bus interface.
CAN Interface
CAN Rx
CAN Tx
CANREC
Can core
CAN_NERR
CAN bus
CANTEC
CANBCR
Transmit buffer
Receive buffer
Control
signals
Status
signals
Data-in[15:0]
Data-out[15:0]
Address[10:0]
Clock
Reset
Interrupt
Wait
CPU interface
CANMCR
CANIRR
CANGSR
CANIMR
CANTXPR
CANTXACK
CANTXCR
CANABACK
CANRXPR
CANRFPR
CANMBIMR
CANUMSR
Mailbox control
CANTCNTR CANTCMR
CANTCR
16-bit timer
These registers are doubled
Mailbox0 Mailbox8 Mailbox16 Mailbox24
Mailbox1 Mailbox9 Mailbox17 Mailbox25
Mailbox2 Mailbox10 Mailbox18 Mailbox26
Mailbox3 Mailbox11 Mailbox19 Mailbox27
Mailbox4 Mailbox12 Mailbox20 Mailbox28
Mailbox5 Mailbox13 Mailbox21 Mailbox29
Mailbox6 Mailbox14 Mailbox22 Mailbox30
Mailbox7 Mailbox15 Mailbox23 Mailbox31
Mailbox0-31 (RAM)
Note: Since the HCAN2 is designed on the basis of a 16-bit bus system, longword (32-bit) accesses are prohibited.
All registers can be accessed with words and mailboxes can be accessed with words or bytes.
Legend:
CANTCNTR
CANTCR
CANTCMR
CANMCR
CANGSR
CANIRR
CANIMR
CANBCR
CANREC
: Timer counter register
: Timer control register
: Timer compare match register
: Master control register
: General status register
: Interrupt request register
: Interrupt mask register
: Bit configuration register
: Receive error counter
CANTEC : Transmit error counter
CANTXPR : Transmit pending request register
CANTXCR : Transmit cancel register
CANTXACK : Transmit acknowledge register
CANABACK : Abort acknowledge register
CANRXPR : Receive data frame pending register
CANRFPR : Remote frame request pending register
CANMBIMR : Mailbox interrupt mask register
CANUMSR : Unread message status register
Figure 22.1 Block Diagram of HCAN2 Module
Rev. 1.0, 02/03, page 758 of 1294