SH7760 Datasheet, PDF (856/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

• CANRFPR0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0
_15 _14 _13 _12 _11 _10
_9
_8
_7
_6
_5
_4
_3
_2
_1
_0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Bit
Bit Name Initial Value R/W
Description
15 to 0 RFPR0[15:0] All 0
R/W*
Remote request pending flags for Mailboxes
15 to 0 respectively.
0: Clearing condition: Write a 1 to this bit.
1: Corresponding Mailbox received Remote
Frame
Setting condition: Completion of remote
frame reception in the corresponding
Mailbox
Note: * Only a write of 1 is allowed to clear the bit.
22.5.13 Mailbox Interrupt Mask Registers 1 and 0 (CANMBIMR1, CANMBIMR0)
The CANMBIMR are two 16-bit read/write registers. The CANMBIMR only prevents the setting
of IRR related to the Mailbox activities (IRR1: Data Frame Received Interrupt, IRR2: Remote
Frame Request Interrupt, IRR8: Mailbox Empty Interrupt, and IRR9: Message Overrun Interrupt).
If a Mailbox is configured as receive, a mask at the corresponding bit position prevents the
generation of receive interrupts (IRR1 and IRR2 and IRR9) but does not prevents the settings of
the corresponding bit in CANRXPR or CANRFPR or CANUMSR. Similarly, when a mailbox has
been configured for transmission, a mask prevents the generation of in Interrupt signal and setting
of an Mailbox Empty Interrupt due to successful transmission or transmission abortion (IRR8),
however, it does not prevent the HCAN2 from clearing the corresponding CANTXPR/CANTXCR
bit and setting the CANTXACK bit for abortion of transmission.
A mask is set by writing a 1 to the corresponding bit for the Mailbox activity to be masked. At
reset, all Mailbox interrupts are masked.
• CANMBIMR1
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1
_15
_14
_13
_12
_11
_10
_9
_8
_7
_6
_5
_4
_3
_2
_1
_0
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.0, 02/03, page 806 of 1294