SH7760 Datasheet, PDF (295/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit
Name Value R/W Description
19
BREQEN 0
R/W BREQ Enable
Indicates whether off-chip requests can be accepted.
BREQEN is initialized to the off-chip request acceptance
disabled state by a power-on reset.
0: Off-chip requests are not accepted
1: Off-chip requests are accepted
18

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
17
MEMMPX 0
R/W Area 1 to 6 MPX Bus Setting
Sets the MPX interface when areas 1 to 6 are specified
as SRAM interface (or burst ROM interface). This bit is
initialized by a power-on reset.
0: SRAM interface (or burst ROM interface) is selected
when areas 1 to 6 are specified as SRAM interface (or
burst ROM interface)
1: MPX interface is selected when areas 1 to 6 are
specified as SRAM interface (or burst ROM interface)
16
DMABST 0
R/W DMAC Burst Mode Transfer Priority Setting
Specifies the priority of burst mode transfers by the
DMAC. When OFF, the priority is as follows: bus
released, refresh, DMAC, CPU. When ON, bus release
and refresh operations are not performed until the end of
the DMAC burst mode transfer. This bit is initialized at a
power-on reset.
0: DMAC burst mode transfer priority setting OFF
1: DMAC burst mode transfer priority setting ON
15
HIZMEM 0
R/W High Impedance (High-Z) Control
Specifies the state of address and other signals (A[25:0],
BS, CSn, RD/WR, CE2A, CE2B) in software standby
mode and the bus-released state.
0: The A[25:0], BS, CSn, RD/WR, CE2A, and CE2B
signals made to the high-impedance state in software
standby mode and the bus-released state
1: The A[25:0], BS, CSn, RD/WR, CE2A, and CE2B
signals driven in software standby mode and made to
the high-impedance state in the bus-released state
Rev. 1.0, 02/03, page 245 of 1294