SH7760 Datasheet, PDF (211/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

7.6.5 Summary of Memory-Mapping of OC
The address ranges to which the OC is memory-mapped in double-size cache mode of this LSI are
summarized below in the example of data array access.
• In normal mode (ORA = 0 in CCR)
H'F500 0000 to H'F500 3FFF (16 kbytes ): Way 0 (entries 0 to 511)
H'F500 4000 to H'F500 7FFF (16 kbytes ): Way 1 (entries 0 to 511)
In the same pattern, shadows of the cache area are created in 32-kbyte blocks until H'F5FF
FFFF.
• In RAM mode (ORA = 1 in CCR)
H'F500 0000 to H'F500 1FFF (8 kbytes ): Way 0 (entries 0 to 255)
H'F500 2000 to H'F500 3FFF (8 kbytes ): Way 1 (entries 0 to 255)
In the same pattern, shadows of the cache area are created in 16-kbyte blocks until H'F5FF
FFFF.
7.7 Store Queues
This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external
memory. If the SQs are not used, power-down modes, in which SQ functions are stopped, can be
used to reduce power consumption. The queue address control registers (QACR0 and QACR1)
cannot be accessed while SQ functions are stopped. See section 14, Power-Down Modes, for the
procedure for stopping SQ functions.
7.7.1 SQ Configuration
There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 7.13. These two store
queues can be set independently.
SQ0 ^{SQ0[0] SQ0[1] SQ0[2] SQ0[3] SQ0[4] SQ0[5] SQ0[6] SQ0[7]}
SQ1 ^{SQ1[0] SQ1[1] SQ1[2] SQ1[3] SQ1[4] SQ1[5] SQ1[6] SQ1[7]}
4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes
Figure 7.13 Store Queue Configuration
Rev. 1.0, 02/03, page 161 of 1294