SH7760 Datasheet, PDF (845/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
0
IRR0
1
R/W Reset/Halt/Sleep Interrupt Flag
Indicates that the CAN Interface has been reset
or halted and the HCAN2 is now in Configuration
mode or HCAN2 is asleep. An interrupt signal will
be generated through this bit to notify the change
of the HCAN2’s state to the host processor if a
MCR0 (Software reset) or MCR1 (Halt) or MCR5
(Sleep) request is made. The GSR may be read
after this bit is set to figure out which state
HCAN2 is in.
Important: When a Sleep mode request needs to
be made, the Halt mode should be used
beforehand. Refer to the MCR5 description.
0: Clearing condition: Write a 1 to this bit.
1: Transition to Software reset mode, Halt mode,
or Sleep mode.
Setting condition: When reset/halt processing
completed after Software reset (MCR0) or Halt
mode (MCR1) or Sleep mode (MCR5) is
requested.
22.5.5 Interrupt Mask Register (CANIMR)
CANIMR is a 16-bit register that prevents all interrupts corresponding interrupts in the CANIRR
from generating on output signal on the IRQ. An interrupt request is masked if the corresponding
bit position is set to 1. This register can be read or written at any time. The CANIMR directly
controls the generation of IRQ, but does not prevent the setting of the corresponding bit in the
CANIRR.
Bit:
Initial value:
R/W:
15 14 13 12 11
- IMR14 IMR13 IMR12 -
1
1
1
1
1
R R/W R/W R/W R
10 9
8
7
6
5
4
3
2
1
0
- IMR9 IMR8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 IMR0
1
1
1
1
1
1
1
1
1
1
1
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.0, 02/03, page 795 of 1294