SH7760 Datasheet, PDF (51/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Section 1 Overview
This LSI is a microcomputer, featuring an LCD controller, USB host, and other peripheral
functions. The SuperH RISC engine is a Hitachi-original 32-bit RISC (Reduced Instruction Set
Computer) microcomputer. The SuperH RISC engine employs a fixed-length 16-bit instruction
set, allowing an approximately 50% reduction in program size over a 32-bit instruction set.
This LSI features the SH-4 CPU, which at the object code level is upwardly compatible with the
SH-1, SH-2, and SH-3 microcomputers. This LSI has an instruction cache, an operand cache that
can be switched between copy-back and write-through modes, a 4-entry full-associative
instruction TLB (translation look aside buffer), and MMU (memory management unit) with 64-
entry full-associative shared TLB. The sizes of the instruction cache and operand cache are 16
kbytes and 32 kbytes.
This LSI also features the bus state controller (BSC) that can connect to synchronous DRAM.
Also, because of its on-chip functions, such as an LCD controller, a USB host, timers, and serial
communication functions, required for multimedia and OA equipment, this LSI enables a dramatic
reduction in system costs.
Note: SuperH^TM is a trademark of Hitachi, Ltd.
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