SH7760 Datasheet, PDF (873/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Section 23 Hitachi Serial Protocol Interface (HSPI)
This LSI incorporates one channel of the Hitachi Serial Protocol Interface (HSPI).
23.1 Features
The HSPI has the following features.
• Operating mode: Master mode or Slave mode.
• The transmit and receive sections within the module are double buffered to allow duplex
communication.
• A flexible peripheral clock division strategy allows a wide range of bit rates to be supported.
• The programmable clock control logic allows setting for two different transmit protocols and
accommodates transmit and receive functions on either edge of the serial bit clock.
• Error detection logic is provided for warning of the receive buffer overflow.
• The HSPI has a facility to generate the chip select signal to slave modules when configured as
a master mode either automatically as part of the data transfer process, or under the manual
control of the host processor.
• The HSPI supports DMA transfer of both receive and transmit data independently via two
DMA channels if implemented in the system.
Rev. 1.0, 02/03, page 823 of 1294