SH7760 Datasheet, PDF (340/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

When the SRAM interface is in use, a bus width of 8, 16, or 32 bits is selectable with bits
A5SZ1 and A5SZ0 in BCR2. When the burst ROM interface is in use, a bus width of 8, 16, or
32 bits is selectable with bits A5SZ1 and A5SZ0 in BCR2. When the MPX interface is in use,
a bus width of 32 bits should be selected by bits A5SZ1 and A5SZ0 in BCR2. When the
PCMCIA interface is in use, select 8 or 16 bits by bits A5SZ1 and A5SZ0 in BCR2.
When area 5 is accessed while the SRAM interface is in use, the CS5 signal is asserted. the RD
signal, which can be used as OE, and write control signals WE0 to WE3 are asserted. While
the PCMCIA interface is in use, the CE1A and CE2A signals, the RD signal, which can be
used as OE, the WE1, WE2, WE3, and WE0 signals, which can be used as WE, ICIORD,
ICIOWR, and REG, respectively, are asserted.
As regards the number of bus cycles, 0 to 15 wait cycles is selectable with bits A5W2 to
A5W0 in WCR2. In addition, any number of wait cycles can be inserted in each bus cycle by
the external wait pin (RDY).
When the burst ROM interface is in use, the number of bus cycles for burst transfer is selected
in the range of 2 to 9 according to the number of wait cycles.
The setup time of the address and CS signal with respect to the read/write strobe can be
specified by bit A5S0 in WCR3 within a range of 0 to 1 cycle. The data-hold time of the
address and CS signal with respect to the read/write strobe can be specified by bits A5H1 and
A5H0 within a range of 0 to 3 cycles.
For a PCMCIA interface, the setup time of the address, CE1A, and CE2A signals with respect
to the read/write strobe can be specified by bits A5TED1 and A5TED0 in PCR within a range
of 0 to 15 cycles. The hold time of the address, CE1A, and CE2A signals can be specified by
bits A5TEH1 and A5TEH0 in PCR within a range of 0 to 15 cycles. The number of wait cycles
can be specified by bits A5PCW1 and A5PCW0 within a range of 0 to 50 cycles. The number
of wait cycles specified by PCR is added to the value specified by WCR2.
(7) Area 6
For area 6, off-chip address bits A28 to A26 are 110.
The interfaces that can be set for this area are SRAM, MPX, burst ROM, and PCMCIA.
When the SRAM interface is in use, a bus width of 8, 16, or 32 bits is selectable with bits
A6SZ1 and A6SZ0 in BCR2. When the burst ROM interface is in use, a bus width of 8, 16, or
32 bits is selectable with bits A6SZ1 and A6SZ0 in BCR2. When the MPX interface is in use,
a bus width of 32 bits should be selected by bits A6SZ1 and A6SZ0 in BCR2. When the
PCMCIA interface is in use, select 8 or 16 bits by bits A6SZ1 and A6SZ0 in BCR2.
Rev. 1.0, 02/03, page 290 of 1294