SH7760 Datasheet, PDF (62/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

1.4 Pin Description
Table 1.1 lists the pin configuration of this LSI. In the I/O column, I, O, and IO indicate input,
output, and input/output, respectively. In the GPIO column, O indicates a pin which also functions
as a general I/O port.
Table 1.1 Pin Configuration
Pin No. Pin Name
A1
EXTAL
A2
XTAL
A3
VDD-CPG
A4
VDD-PLL1
A5
SSI0_SCK/HAC_SD_IN0/BS2
A6
HSPI_TX/SIM_D/MCDAT
A7
HSPI_CLK/SIM_CLK/MCCLK
A8
CMT_CTR1
A9
CMT_CTR3
A10
SCIF2_CLK
A11
SCIF2_TXD
A12
SCIF2_RXD
A13
SCIF2_CTS
A14
SCIF2_RTS
A15
SCIF0_CLK
A16
SCIF0_TXD
A17
MD4/CE2B
A18
DACK0
A19
VDD-PLL3
A20
UCLK
B1
RESET
B2
VSS-CPG
B3
VDD-PLL2
B4
VSS-PLL1
B5
SSI0_WS/HAC_SYNC0
I/O
Function
GPIO
I
External input clock/crystal resonator
O
Crystal resonator

CPG VDD

PLL1 VDD
IO/I/O SSI serial clock input/HAC serial data/bus start 2 Ο
O/IO/IO HSPI transmit data/SIM data transfer/MMCIF data Ο
IO/O/O HSPI serial clock/SIM clock/MMCIF clock
Ο
IO
CMT counter
Ο
IO
CMT counter
Ο
IO
SCIF serial clock
Ο
O
SCIF transmit data
Ο
I
SCIF receive data
Ο
IO
SCIF modem control
Ο *¹
IO
SCIF modem control
Ο *²
IO
SCIF serial clock
Ο
O
SCIF transmit data
Ο
IO
Mode control 4/PCMCIA-CE
O
DMAC0 bus acknowledge

PLL3 VDD
I
USB operation clock
Ο
I
Reset

CPG GND

PLL2 VDD

PLL1 VSS
IO/O
SSI word selection/HAC from sync output
Ο
Rev. 1.0, 02/03, page 12 of 1294