SH7760 Datasheet, PDF (694/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
2
SDT
0
R/W* Slave Data Transmitted
A byte of data has been transmitted on the bus.
This status bit becomes active after the falling
edge of SCL during the last data bit.
1
SDR
0
R/W* Slave Data Received
A byte of data has been received from the bus
and is available in the receive data register. This
bit becomes active after the falling edge of SCL
during the last data bit. After data has been read
from the ICRXD register, this bit must be reset in
single buffer mode. This bit is not used in the
FIFO buffer mode.
When SDBS is set to 1, SCL will be held low from
the moment the receive data register acquires the
data packet up until SDR is cleared.
0
SAR
0
R/W* Slave Address Received
Indicates that the slave has recognized its own
address on the bus (defined by the contents of
the slave address register). If the general call
acknowledgement enable bit in the slave control
register is enabled, then this status bit could also
indicate the reception of a general call address on
the bus. In that case, bit GCAR of this register is
used to differentiate the receipt of a general call
address. Bit STM indicates whether the access is
a read (high) or a write (low). This status becomes
active after the falling edge of SCL during the last
address bit. The slave holds SCL low at the start
of the ACK phase until this bit is reset by
software.
Note: * This bit can be written or read. When 0 is written to, the bit is initialized. When 1 is written to,
it is ignored.
Rev. 1.0, 02/03, page 644 of 1294