SH7760 Datasheet, PDF (36/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Figure 19.3 Master Data Transmit format ..................................................................................664
Figure 19.4 Master Data Receive format ....................................................................................664
Figure 19.5 Combination Transfer Format of Master Transfer ..................................................665
Figure 19.6 10-Bit Address Data Transfer Format .....................................................................665
Figure 19.7 10-Bit Address Data Receive Format ......................................................................666
Figure 19.8 10-Bit Address Transmit/Receive Combination Format .........................................666
Figure 19.9 Data Transfer Mode Timing Chart ..........................................................................668
Figure 19.10 Data Receive Mode Timing Chart.........................................................................669
Figure 19.11 Operational Example of One-byte Data Transmission ..........................................676
Figure 19.12 Operational Example of Two-byte Data Transmission .........................................677
Figure 19.13 Operational Example of Three-byte Data Transmission .......................................678
Figure 19.14 Operation Example of Four or More Byte Data Transmission..............................678
Section 20 Serial Sound Interface (SSI) Module
Figure 20.1 Block Diagram of SSI Module ................................................................................682
Figure 20.2 Philips Format (with no Padding)............................................................................697
Figure 20.3 Philips Format (with Padding).................................................................................698
Figure 20.4 Sony Format (with Serial Data First, Followed by Padding Bits) ...........................698
Figure 20.5 Matsushita Format (with Padding Bits First, Followed by Serial Data) ..................699
Figure 20.6 Multichannel Format (4 Channels, No Padding) .....................................................701
Figure 20.7 Multichannel Format (6 Channels with High Padding)...........................................701
Figure 20.8 Multichannel Format
(8 Channels, with Padding Bits First, Followed by Serial Data, with Padding) ......702
Figure 20.9 Basic Sample Format
(Transmit Mode with Example System/Data Word Length)...................................702
Figure 20.10 Inverted Clock .......................................................................................................703
Figure 20.11 Inverted Word Select.............................................................................................703
Figure 20.12 Inverted Padding Polarity ......................................................................................703
Figure 20.13 Padding Bits First, Followed by Serial Data, with Delay ......................................704
Figure 20.14 Padding Bits First, Followed by Serial Data, without Delay .................................704
Figure 20.15 Serial Data First, Followed by Padding Bits, without Delay.................................704
Figure 20.16 Parallel Right Aligned with Delay.........................................................................705
Figure 20.17 Mute Enabled ........................................................................................................705
Figure 20.18 Compressed Data Format, Slave Transmitter, Burst Mode Disabled ....................706
Figure 20.19 Compressed Data Format, Slave Transmitter, and Burst Mode Enabled ..............706
Figure 20.20 Transition Diagram between Operation Modes.....................................................708
Figure 20.21 Transmission Using DMA Controller ...................................................................709
Figure 20.22 Transmission using Interrupt Data Flow Control ..................................................710
Figure 20.23 Reception using DMA Controller..........................................................................712
Figure 20.24 Reception using Interrupt Data Flow Control........................................................713
Section 21 USB Host Module (USB)
Figure 21.1 Block Diagram of USB Host Module......................................................................716
Figure 21.2 Memory Map of Shared Memory ............................................................................754
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