SH7760 Datasheet, PDF (973/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit
Name Value R/W Description
7 to 0 RSPR All 0
R/W These bits are cleared to H'00 by writing an arbitrary value.
RSPR0 to RSPR16 comprise a continuous 17-byte shift
register.
26.3.7 Command Start Register (CMDSTRT)
CMDSTRT is an 8-bit readable/writable register that triggers the start of command transmission,
representing the start of a command sequence. The following operations should have been
completed before the command sequence starts.
• Analysis of prior command response, clearing the command response register write if
necessary
• Analysis/transfer of receive data of prior command if necessary
• Preparation of transmit data of the next command if necessary
• Setting of CMDTYR, RSPTYR, and TBCR
• Setting of CMDR0 to CMDR4
The CMDR0 to CMDR4, CMDTYR, RSPTYR, and TBCR registers should not be changed
until command transmission has ended (the CWRE flag in CSTR has been set to 1).
Command sequences are controlled by the sequencers in both the MMCIF side and the MMC card
side. Normally, these operate synchronously. However, if an error occurs or a command is aborted,
these may become temporarily unsynchronized. Be careful when setting the CMDOFF bit in
OPCR, issuing the CMD12 command, or processing an error in MMC mode. A new command
sequence should be started only after the end of the command sequence on both the MMCIF and
card sides is confirmed.
Bit: 7
6
5
-
-
-
Initial value: 0
0
0
R/W: R
R
R
4
3
-
-
0
0
RR
2
1
0
-
- _START
0
0
0
R R R/W
Bit
7 to 1
Bit
Name
—
Initial
Value
All 0
0
START 0
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Starts command transmission when 1 is written. This bit
is automatically cleared. When 0 is written to this bit, its
previous value is retained.
Rev. 1.0, 02/03, page 923 of 1294