SH7760 Datasheet, PDF (434/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

11.3.6 DMA Request Resource Selection Registers (DMARSRA, DMARSRB)
DMARSRA and DMARSRB are 32-bit readable/writable registers that specify the transfer request
source for each channel, together with the RS bits in each CHCRn. When the channel is not used,
or DMA transfer initiated by an auto-request or a TMU input capture interrupt is used, the
DMARSR corresponding to that channel should be set to H'00.
To resume a DMA transfer that has stopped due to an address error (AE = 1 in DMAOR) or an
NMI interrupt (NMIF = 1 in DMAOR), re-specify this register value, regardless of whether or not
a transfer request source to any channel has been changed, before specifying AE = 0 in DMAOR
or NMIF = 0 in DMAOR.
• DMARSRA
Bit:
Initial value:
R/W:
31
CH0
WEN
0
R/W
30
CH0
RS6
0
R/W
29
CH0
RS5
0
R/W
28
CH0
RS4
0
R/W
27
CH0
RS3
0
R/W
26
CH0
RS2
0
R/W
25
CH0
RS1
0
R/W
24
CH0
RS0
0
R/W
23
CH1
WEN
0
R/W
22
CH1
RS6
0
R/W
21
CH1
RS5
0
R/W
20
CH1
RS4
0
R/W
19
CH1
RS3
0
R/W
18
CH1
RS2
0
R/W
17
CH1
RS1
0
R/W
16
CH1
RS0
0
R/W
Bit:
Initial value:
R/W:
15
CH2
WEN
0
R/W
14
CH2
RS6
0
R/W
13
CH2
RS5
0
R/W
12
CH2
RS4
0
R/W
11
CH2
RS3
0
R/W
10
CH2
RS2
0
R/W
9
CH2
RS1
0
R/W
8
CH2
RS0
0
R/W
7
CH3
WEN
0
R/W
6
CH3
RS6
0
R/W
5
CH3
RS5
0
R/W
4
CH3
RS4
0
R/W
3
CH3
RS3
0
R/W
2
CH3
RS2
0
R/W
1
CH3
RS1
0
R/W
0
CH3
RS0
0
R/W
• DMARSRB
Bit:
Initial value:
R/W:
31
CH4
WEN
0
R/W
30
CH4
RS6
0
R/W
29
CH4
RS5
0
R/W
28
CH4
RS4
0
R/W
27
CH4
RS3
0
R/W
26
CH4
RS2
0
R/W
25
CH4
RS1
0
R/W
24
CH4
RS0
0
R/W
23
CH5
WEN
0
R/W
22
CH5
RS6
0
R/W
21
CH5
RS5
0
R/W
20
CH5
RS4
0
R/W
19
CH5
RS3
0
R/W
18
CH5
RS2
0
R/W
17
CH5
RS1
0
R/W
16
CH5
RS0
0
R/W
Bit:
Initial value:
R/W:
15
CH6
WEN
0
R/W
14
CH6
RS6
0
R/W
13
CH6
RS5
0
R/W
12
CH6
RS4
0
R/W
11
CH6
RS3
0
R/W
10
CH6
RS2
0
R/W
9
CH6
RS1
0
R/W
8
CH6
RS0
0
R/W
7
CH7
WEN
0
R/W
6
CH7
RS6
0
R/W
5
CH7
RS5
0
R/W
4
CH7
RS4
0
R/W
3
CH7
RS3
0
R/W
2
CH7
RS2
0
R/W
1
CH7
RS1
0
R/W
0
CH7
RS0
0
R/W
Rev. 1.0, 02/03, page 384 of 1294