SH7760 Datasheet, PDF (831/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
5
MCR5
0
R/W Sleep Mode
Enables/disables Sleep mode transition. If this bit
is set, the Sleep Mode is enabled. The HCAN2
waits for the completion of the current bus activity
before shutting down. Until this mode is
terminated HCAN2 will ignore all CAN bus
activities. The two Error Counters (TEC and REC)
will remain the same values during Sleep mode.
Sleep mode will be exited in two ways:
• By writing a 0 to this bit.
• If MCR7 is enabled after detecting the
dominant bit on the CAN bus.
When leaving this mode, the HCAN2 will
synchronize to the CAN bus (by checking for 11
recessive bits) before re-initializing. This means
that, when the second method above is used, the
HCAN2 will miss the first message to receive,
however, CAN transceivers have the same
feature, and the software needs to be designed in
this manner.
Important: This mode is same as setting the
module to the Halt mode and stopping the
clock. This means that, the interrupt is
generated from IRR0 when entering the
Sleep mode. During the Sleep mode, only
the MPI block is accessible, i.e.,
CANMCR/CANGSR/CANIRR/CANIMR
are accessible. However, for example,
IRR1 cannot be cleared as it is an OR’ed
signal of CANRXPR that cannot be
cleared during the Sleep mode, therefore,
it is recommended to set the Halt mode
first and then transit to the Sleep mode.
0: HCAN2 sleep mode is released.
1: Transition to HCAN2 sleep mode is enabled.
Rev. 1.0, 02/03, page 781 of 1294