SH7760 Datasheet, PDF (1032/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

27.3.7 MFI Address Register (MFIADR)
The MFIADR is a 32-bit register which indicates the address in the MFRAM to be accessed by
the external device via the MFI.
Specifying continuous access to the MFRAM in the LOCK bit in MFIMCR automatically
performs auto-increment (+4) or auto-decrement (-4) of the address according to the AI/AD bit in
MFIMCR, and updates MFIADR each time the external device accesses the MFRAM.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
- A10 A9 A8 A7 A6 A5 A4 A3 A2
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R
R
Bit
Initial
Bit
Name Value R/W Description
31 to 11 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
10 to 2 A10
to
A2
All 0
R/W*
Address
Specifies the memory space in the 2-kbyte MFRAM to
be accessed by the external device via the MFI, with 32-
bit alignment.
1, 0

All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Note: * The external device can write to these bits via the MFI. The on-chip CPU cannot write to
these bits.
Rev. 1.0, 02/03, page 982 of 1294