SH7760 Datasheet, PDF (172/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

MMUCR
31
26 25 24 23
18 17 16 15
10 9 8 7
3210
LRUI
—
URB
—
URC
SV
—
TI — AT
Entry specification
SQMD
PTEH
31
VPN
10 9 8 7
—
0
ASID
PTEL
31 2928
—
10 9 8 7 6 5 4 3 2 1 0
PPN
— V SZ1 PR[1:0] SZ0 C D SH WT
PTEA
31
432 0
—
TC SA[2:0]
Write
Entry 0
Entry 1
Entry 2
ASID [7:0] VPN [31:10] V
ASID [7:0] VPN [31:10] V
ASID [7:0] VPN [31:10] V
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC
Entry 63 ASID [7:0] VPN [31:10] V
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC
UTLB
Figure 6.11 Operation of LDTLB Instruction
6.4.4 Hardware ITLB Miss Handling
In an instruction access, this LSI searches the ITLB. If it cannot find the necessary address
translation information (ITLB miss occurred), the UTLB is searched by hardware, and if the
necessary address translation information is present, it is recorded in the ITLB. This procedure is
known as hardware ITLB miss handling. If the necessary address translation information is not
found in the UTLB search, an instruction TLB miss exception is generated and processing passes
to software.
Rev. 1.0, 02/03, page 122 of 1294