SH7760 Datasheet, PDF (522/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

12.4.1 Frequency Control Register (FRQCR)
FRQCR is a 16-bit readable/writable register that specifies use/non-use of clock output from the
CKIO pin, on/off control of PLL circuits 1 and 2, and the frequency division ratios of the CPU
clock, bus clock, and peripheral clock. FRQCR can only be accessed in words.
FRQCR is initialized only by a power-on reset via the RESET pin. The initial value of each bit is
determined by the clock operating mode.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
CKO
EN
PLL1
EN
PLL2
EN
IFC2
IFC1
IFC0 BFC2 BFC1 BFC0 PFC2 PFC1 PFC0
Initial value: 0
0
0
0
1
1
1
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 12 —
11
CKOEN
10
PLL1EN
9
PLL2EN
Initial Value R/W
All 0
R
1
R/W
1
R/W
1
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Clock Output Enable
Specifies whether a clock is output from the CKIO
pin or the CKIO pin is placed in the high-
impedance state. When the CKIO pin goes to the
high-impedance state, operation continues at the
operating frequency before this state was
entered. When the CKIO pin becomes high-
impedance, it is pulled up. Note that the CKIO pin
is not pulled up in hardware standby mode.
0: CKIO pin goes to high-impedance state
1: Clock is output from CKIO pin
PLL Circuit 1 Enable
Specifies whether PLL circuit 1 is on or off.
0: PLL circuit 1 is not used
1: PLL circuit 1 is used
PLL Circuit 2 Enable
Specifies whether PLL circuit 2 is on or off.
0: PLL circuit 2 is not used
1: PLL circuit 2 is used
Rev. 1.0, 02/03, page 472 of 1294