SH7760 Datasheet, PDF (449/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
2
TAR
0
R/W HAC/SSI Transmit DMA Auto Reload Setting
Specifies the use or unuse of auto address reload
to continue a DMA transfer when the number of
bytes in the transmit DMA transfer reaches the
number of transfer bytes specified by
DMAARXTCRn.
0: Address of transmit DMA not auto reloaded
1: Address of transmit DMA auto reloaded
1
TDS
0
R/W HAC/SSI Transmit DMA Termination
Setting this bit to 1 forcibly terminates a transmit
DMA transfer.
• When writing
0: Write operation is ignored
1: Transmit DMA transfer is forcibly terminated
• When reading
0: Transfer is completed
1: Transfer is being performed
0
TDE
0
R/W HAC/SSI Transmit DMA Transfer Activation
Control
Controls the transmit DMA transfer activation.
Write operation is ignored during transfer. To
reactivate a transmit DMA transfer, read this bit as
0 and then write 1 to it.
• When writing
0: Write operation is ignored
1: Transmit DMA transfer is activated
• When reading
0: Transfer is completed
1: Transfer is being performed
Rev. 1.0, 02/03, page 399 of 1294