SH7760 Datasheet, PDF (345/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(2) Wait State Control
Wait-state insertion for the SRAM interface can be controlled by WCR2. If the wait-control
bits for each area in WCR2 are not zero, a software wait is inserted in accordance with the
wait-control bits. For details, see section 10.5.6, Wait Control Register 2 (WCR2).
A specified number of Tw cycles are inserted as wait cycles using the SRAM interface wait
timing shown in figure 10.10.
CKIO
A25–A0
CSn
RD/WR
RD
D31–D0
(read)
WEn
D31–D0
(write)
BS
T1
Tw
T2
RDY
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
Note: For DACKn, an example is shown where the acknowledge level (AL) bit in CHCRn
of the DMAC is cleared to 0.
Figure 10.10 SRAM Interface Wait Timing (Software Wait Only)
Rev. 1.0, 02/03, page 295 of 1294