SH7760 Datasheet, PDF (699/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

19.3.6 Master Status Register (ICMSR)
The status bits of the master status register (bits 0 to 6) are cleared by writing 0 to the respective
status bit positions in the reception states. Each status bit remains 1 until reset by writing 0.
Bit: 31 30
-
-
Initial value: 0
0
R/W: R
R
Bit: 15 14
-
-
Initial value: 0
0
R/W: R
R
Bit
Bit Name
31 to 7 
6
MNR
5
MAL
4
MST
29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
- MNR MAL MST MDE MDT MDR MAT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Initial Value R/W Description
All 0
R
Reserved
These bits are always read as 0, and the write
value should always be 0.
0
R/W* Master NACK Received
MNR = 1 indicates that the master has received a
NACK response (SDA is high during the
acknowledge cycle on the bus) during an address
or data transmission.
0
R/W* Master Arbitration Lost
MAL = 1 in the multiple-master system indicates
that the master has lost bus arbitration for other
masters. In this case, MIE is reset and master
interface is disabled.
0
R/W* Master Stop Transmission
MST = 1 indicates that the master has sent a stop
onto the bus. A stop can be sent either as a result
of the setting of the forced stop bit in the control
register, or from a NACK being received from a
slave during data packet reception from a slave.
Rev. 1.0, 02/03, page 649 of 1294