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SH7760 Datasheet, PDF (361/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D31–D0
(read)
Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Td5 Td6 Td7 Td8
H/L
H/L
c1
c5
c1 c2 c3 c4 c5 c6 c7 c8
BS
CKE
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.21 Burst Read Timing (RAS Down, Same Row Address)
Rev. 1.0, 02/03, page 311 of 1294