SH7760 Datasheet, PDF (712/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

19.4.4 Software Status Interlocking
To make software interface to the I²C bus interface module as robust and simple as possible, some
statuses are interlocked in the master and slave interface operations. The status bits involved are
described below.
(1) MDR and SDR (Single Buffer Mode)
MDR and SDR are set to 1 when data is received. Clear these bits to 0 after reading the receive
data register. If data is received while MDR and SDR are 1, hardware recognizes that unread
data remains in the receive data register, automatically holds SCL at low level and suspends
data transfer. In this case, clearing these bits to 0 after reading the receive data will resume
transfer.
When receiving data consecutively, be sure to clear MDR and SDR to 0 after reading the
receive data register.
(2) MDE and SDE (Single Buffer Mode)
When the slave or master is about to start transmission of data (from the transmit data register)
onto the I²C bus, the MDE and SDE status bits may still remain 1. In such case, the SCL line
must be held low until these bits are reset to 0. The MDE and SDE bits being set to 1 indicate
that the data has already been transmitted from the transmit data register onto the I²C bus.
To write data into the transmit data register that is ready for the next transmission, the software
must clear MDE and SDE to 0. However, this is not required for the first byte transmission
onto the bus.
(3) MAL
When the master has lost arbitration, the MAL bit in the master status register is set to 1 and
the MIE bit in the master control register is reset to 0. At this point, the master mode is
disabled and the I²C bus interface is set to operate in the slave mode. When master operation is
restarted, data transfer from the master begins after the MAL bit has been cleared to 0.
(4) SAR
The SAR status bit is set to 1 when the slave has recognized its address output to the I²C bus.
At this point, the slave interface drives the SCL line to be low until the SAR status bit is reset
to 0.
This is particularly important when a slave transmit is about to take place on the bus. When the
slave transmits the data from the transmit data register, the software responds to the SAR status
by writing the required data into the transmit data register and resetting the SAR status bit to 0.
This allows the slave interface to carry on access.
When the slave is about to receive data, the software may not have completed reading of data
loaded by the previous access from the receive data register. The problem is that the new
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