SH7760 Datasheet, PDF (464/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Since in dual address mode, data corresponding to the size specified by the TS bit in CHCRn is
read from the transfer source in the data read cycle and is written to the transfer destination in
the data write cycle, it is transferred in two bus cycles. In this process, the transfer data is
temporarily stored in the data buffer in the bus state controller (BSC).
In a transfer between external memories such as that shown in figure 11.8, data is read from
external memory into the BSC’s data buffer in the read cycle, then written to the other external
memory in the write cycle. Figure 11.9 shows the timing for this operation. The DACK output
timing is the same as that of CSn in a read or write cycle specified by the AM bit in CHCRn.
DMAC
SAR
DAR
Memory
Transfer source
module
BSC ^{Data buffer}
Transfer destination
module
Taking the SAR value as the address, data is read from the transfer source module
and stored temporarily in the data buffer in the bus state controller (BSC).
1st bus cycle
DMAC
SAR
DAR
BSC Data buffer
Memory
Transfer source
module
Transfer destination
module
Taking the DAR value as the address, the data stored in the BSC’s data buffer is
written to the transfer destination module.
2nd bus cycle
Figure 11.8 Operation in Dual Address Mode
Rev. 1.0, 02/03, page 414 of 1294