SH7760 Datasheet, PDF (350/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

The negate timing for CS1 and RD should be set as follows:
Number of Inserted Wait
Cycles during Data Holding
0
1
2
3
A1H[1:0]
0
0
0
1
1
0
1
1
CSH[1:0]
0
0
0
1
1
0
1
1
10.6.4 Synchronous DRAM Interface
(1) Synchronous DRAM Connection System
Since synchronous DRAM is selectable with the CS signal, it can be connected to off-chip
memory space areas 2 and 3 and share usage of RAS and other control signals. If bits
DRAMTP2 to DRAMTP0 in BCR1 are 010, area 3 becomes a synchronous DRAM interface.
If set to 011, areas 2 and 3 both become synchronous DRAM interfaces.
This LSI supports burst read and burst write modes with a burst length of 4 as a synchronous
DRAM operating mode. The data bus width is 32 bits, and the SZ bits in MCR must be set to
11. A 32-byte burst transfer is performed in a cache fill/copy-back cycle. For write operations
in the write-through area and read/write operations in the non-cacheable area, 16-byte data is
also read in a single read because the synchronous DRAM is accessed by burst read/write
operations with a burst length of 4. Transfer of 16-byte data is also performed in a single write,
but DQMn is not asserted when unnecessary data is transferred.
This LSI also supports read and burst read and burst write modes with a burst length of 8 as a
synchronous DRAM operating mode. The data bus width is 32 bits, and the SZ bits in MCR
must be set to 11. A 32-byte burst transfer is performed in a cache fill/copy-back cycle. For
write operations in the write-through area and read/write operations in the non-cacheable area,
32-byte data is also read in a single read because the synchronous DRAM is accessed by burst
read/write operations with a burst length of 8. Transfer of 32-byte data is also performed in a
single write, but DQMn is not asserted when unnecessary data is transferred. For details of
setting a burst length of 8, refer to (11) Changing the Burst Length, in section 10.6.4. For
details of burst length, refer to section 10.5.11, Synchronous DRAM Mode Register (SDMR),
and (10) Power-on Sequence, in section 10.6.4.
Rev. 1.0, 02/03, page 300 of 1294