SH7760 Datasheet, PDF (714/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 19.4 Legend in I²C Bus Data Format
Symbol
S
SLA
R/W
A
DATA
P
Description
Start condition. The master device drives SDA from high to low level while SCL
is high level.
Slave address. The slave address is selected by the master device.
Indicates the direction of data transfer: from the slave device to the master
device when R/W is 1, or from the master device to the slave device when
R/W is 0.
Data acknowledge. Data receive device drives SDA to low level. The slave
device returns a data acknowledge signal in master transmit mode.
Transfer data. The data consists of 8 bits, which are transferred from MSB.
Stop condition. The master device drives SDA from low to high level while SCL
is high level.
19.4.6 7-Bit Address Format
Figure 19.3 shows the format of data transfer from the master to the slave device (master data
transmit format). Figure 19.4 shows the data transfer format (master data receive format) in which
the master device read data on and after the second byte from the slave device.
S SLAVE ADDRESS R/W A DATA A DATA
A/A P
0 (Write)
Data transferred
(n bytes + ACKNOWLEDGE)
: From MASTER to SLAVE
: From SLAVE to MASTER
A = ACKNOWLEDGE (SDA LOW)
A = NOT ACKNOWLEDGE (SDA HIGH)
S = Start condition
P = Stop condition
Figure 19.3 Master Data Transmit format
S SLAVE ADDRESS R/W A
1 (Read)
DATA A DATA
A/A P
Data transferred
(n bytes + ACKNOWLEDGE)
Figure 19.4 Master Data Receive format
Figure 19.5 shows the combination transfer format in which the data transfer direction changes
during one transfer.
Rev. 1.0, 02/03, page 664 of 1294