SH7760 Datasheet, PDF (567/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

15.4 Operation
Each channel has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR).
Each TCNT performs count-down operation. The channels have an auto-reload function that
allows cyclic count operations, and can also perform external event counting. Channel 2 also has
an input capture function.
15.4.1 Counter Operation
When one of bits STR0 to STR2 in TSTR is set to 1, the TCNT for the corresponding channel
starts counting. When TCNT underflows, the UNF flag in TCR is set. If the UNIE bit in TCR is
set to 1 at this time, an interrupt request is sent to the CPU. At the same time, the value is copied
from TCOR into TCNT, and the count-down continues (auto-reload function).
(1) Example of Count Operation Setting Procedure
Figure 15.2 shows an example of the count operation setting procedure.
Select operation
Select count clock ₍₁₎
Underflow interrupt
generation setting
(2)
(1) Select the count clock with the TPSC2 to TPSC0
bits in TCR. When the external clock (TCLK) is
selected, specify the external clock edge with the
When input capture _{CKEG1 and CKEG0 bits in TCR.}
function is used _{(2) Specify whether an interrupt is to be generated}
Input capture interrupt ₍₃₎
generation setting
on TCNT underflow with the UNIE bit in TCR.
(3) When the input capture function is used, set the
ICPE bits in TCR, including specification of
whether the interrupt function is to be used.
Timer constant
register setting
(4)
(4) Set a value in TCOR.
(5) Set the initial value inTCNT.
(6) Set the STR bit to 1 in TSTR to start the count.
Set initial timer
counter value
(5)
Start count
(6)
Note: When an interrupt is generated, clear the source flag in the interrupt handler. If the interrupt
enabled state is set without clearing the flag, another interrupt will be generated.
Figure 15.2 Example of Count Operation Setting Procedure
Rev. 1.0, 02/03, page 517 of 1294