SH7760 Datasheet, PDF (48/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 28.3 (4) SDBSR Configuration.....................................................................................1000
Table 28.3 (5) SDBSR Configuration.....................................................................................1001
Table 28.3 (6) SDBSR Configuration.....................................................................................1002
Table 28.3 (7) SDBSR Configuration.....................................................................................1003
Table 28.3 (8) SDBSR Configuration.....................................................................................1004
Table 28.3 (9) SDBSR Configuration.....................................................................................1005
Table 28.4 Register Configuration (1) ..................................................................................1005
Table 28.4 Register Configuration (2) ..................................................................................1006
Table 28.4 Register Configuration (3) ..................................................................................1006
Section 29 A/D Converter (ADC)
Table 29.1 Pin Configuration................................................................................................1015
Table 29.2 Register Configuration (1) ..................................................................................1016
Table 29.2 Register Configuration (2) ..................................................................................1016
Table 29.3 Analog Input Channels and Corresponding A/D Data Registers ........................1017
Table 29.4 A/D Conversion Time .........................................................................................1028
Table 29.5 Relationship between Clock Division Ratio and
Usable Input Clock Frequency............................................................................1033
Section 30 LCD Controller (LCDC)
Table 30.1 Pin Configuration................................................................................................1036
Table 30.2 Register Configuration (1) ..................................................................................1037
Table 30.2 Register Configuration (2) ..................................................................................1038
Table 30.3 I/O Clock Frequency and Clock Division Ratio .................................................1040
Table 30.4 Display Resolutions when Using Display Rotation ............................................1064
Table 30.5 Available Power-Supply Control-Sequence Periods at Typical Frame Rates.....1072
Table 30.6 LCDC Operating Modes .....................................................................................1073
Table 30.7 LCD Module Power-Supply States .....................................................................1073
Section 31 User Break Controller (UBC)
Table 31.1 Register Configuration (1) ..................................................................................1091
Table 31.1 Register Configuration (2) ..................................................................................1092
Section 33 Electrical Characteristics
Table 33.1 Absolute Maximum Ratings ...............................................................................1195
Table 33.2 DC Characteristics (T_a=−40 to 85°C) .................................................................1196
Table 33.3 Permissible Output Currents ...............................................................................1198
Table 33.4 Clock Timing ......................................................................................................1198
Table 33.5 Clock and Control Signal Timing .......................................................................1199
Table 33.6 Control Signal Timing ........................................................................................1206
Table 33.7 Bus Timing..........................................................................................................1208
Table 33.8 INTC Module Signal Timing ..............................................................................1241
Table 33.9 DMAC Module Signal Timing ...........................................................................1241
Table 33.10 TMU Module Signal Timing ..............................................................................1242
Rev. 1.0, 02/03, page xlvi of xlviii