SH7760 Datasheet, PDF (1294/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

33.3.8 H-UDI Module Signal Timing
Table 33.12 H-UDI Module Signal Timing
(V_DDQ= 3.0 to 3.6V, V_DD= 1.5V, T_a= −40 to 85°C, C_L= 30pF, PLL2 on)
Module Item
H-UDI Input clock cycle
Input clock pulse width (High)
Input clock pulse width (Low)
Input clock rise time
Input clock fall time
ASEBRK setup time
ASEBRK hold time
TDI/TMS setup time
TDI/TMS hold time
TDO data delay time
ASE-PINBRK pulse width
Notes: 1. t : one CKIO cycle time
cyc
2. t : one Pck cycle time
Pcyc
Symbol
t_TCKcyc
t_TCKH
t_TCKL
t_TCKr
t
TCKf
t_ASEBRKS
t_ASEBRKH
t_TDIS
t_TDIH
t_TDO
t_PINBRK
Min.
50
15
15
—
—
10
10
15
15
0
2
Max.
—
—
—
10
10
—
—
—
—
10
—
Unit
ns
ns
ns
ns
ns
t_cyc
t_cyc
ns
ns
ns
t_Pcyc
Figure
Notes
33.54, 33.56
33.54
33.54
33.54
33.54
33.55
33.55
33.56
33.56
33.56
33.57
t_TCKcyc
t_TCKH
t_TCKL
1/2V_DDQ
V_IH
V_IH
V_IL
V_IL
t_TCKf
V_IH
1/2V_DDQ
t_TCKr
Note: When clock is input from TCK pin.
Figure 33.54 TCK Input Timing
RESET
ASEBRK/
BRKACK
t_ASEBRKS t_ASEBRKH
Figure 33.55 RESET Hold Timing
Rev. 1.0, 02/03, page 1244 of 1294