SH7760 Datasheet, PDF (875/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

23.3 Register Descriptions
The HSPI has the following registers. For details on addresses of these registers and register status
in each processing state, refer to section 32, List of Registers.
Table 23.2 Register Configuration (1)
Register Name
Control register
Status register
System control register
Transmit buffer register
Receive buffer register
Abbrev. R/W P4 Address
SPCR R/W H’FE18 0000
SPSR
R*² H’FE18 0004
SPSCR R/W H’FE18 0008
SPTBR R/W H’FE18 000C
SPRBR R
H’FE18 0010
Area 7 Address
H’1E18 0000
H’1E18 0004
H’1E18 0008
H’1E18 000C
H’1E18 0010
Size
32
32
32
32
32
Sync
Clock
Pck
Pck
Pck
Pck
Pck
Table 23.2 Register Configuration (2)
Register Name
Abbrev.
Power-on
Reset by
RESET
Pin/WDT/
H-UDI
Manual Reset
by RESET
Pin/WDT/
Multiple
Exception
Standby
Sleep
by Sleep
Instruction/
by Software/
Deep Sleep by Hardware Each Module
Control register
SPCR
H’0000 0000*¹ H’0000 0000*¹ Retained
* Retained
Status register
SPSR
H’0000 0120*¹ H’0000 0120*¹ Retained
Retained
System control register
SPSCR H’0000 0040*¹ H’0000 0040*¹ Retained
Retained
Transmit buffer register
SPTBR H’0000 0000*¹ H’0000 0000*¹ Retained
Retained
Receive buffer register
SPRBR H’0000 0000*¹ H’0000 0000*¹ Retained
Retained
Notes: * After exiting hardware standby mode, this LSI enters the power-on reset state caused
by the RESET pin.
1. Reserved bits are read as undefined values.
2. To clear the flag, only 0s are written to bits 4 and 3.
Rev. 1.0, 02/03, page 825 of 1294