SH7760 Datasheet, PDF (1007/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

• The end of the command sequence is detected by poling the BUSY flag in CSTR, data
transfer end interrupt (DTI), or data response interrupt (DRPI).
• The data busy state is checked through DTBUSY in CSTR. If the card is in data busy state,
the end of the data busy state is detected by the data busy end interrupt (DBSYI).
Note: In a write to the card by stream transfer, the MMCIF continues data transfer to the card
even after a FIFO empty interrupt is detected. In this case, complete the command
sequence after at least 24 transfer clock cycles.
Input/output pins
MCCLK
MCCMD
MCDAT
CMDSTRT
(START)
OPCR
(DATAEN)
INTSTR0
(CMDI)
(CRPI)
(DTI)
(DRPI)
(DBSYI)
(FEI)
CSTR
(CWRE)
(BUSY)
(FIFO_EMPTY)
(DTBUSY)
(DTBUSY_TU)
CMD24(WRITE_SINGLE_BLOCK)
Command
Command
response
Command
transmission
started
Write data
Status
Single block write command execution sequence
Busy
(REQ)
Figure 26.15 Example of Command Sequence for Commands with Write Data
(Block Size ≤ FIFO Size)
Rev. 1.0, 02/03, page 957 of 1294