SH7760 Datasheet, PDF (88/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

A A+1 A+2 A+3
31
23
15
7
0
7
07
07
07
0
Address A _{Byte 0 Byte 1 Byte 2 Byte 3}
15
0 15
0
Address A + 4
Word 0
Word 1
31
0
Address A + 8
Longword
A + 11 A + 10 A + 9 A + 8
31
23
15
7
0
7
07
07
07
0
Byte 3 Byte 2 Byte 1 Byte 0 ^{Address A + 8}
15
0 15
0
Word 1
Word 0 Address A + 4
31
Longword
0
Address A
Big endian
Little endian
Figure 2.4 Data Formats in Memory
Note: This LSI does not support endian conversion for the 64-bit data format. Therefore, if
double-precision floating-point format (64-bit) access is performed in little endian mode,
the upper and lower 32 bits will be reversed.
2.5 Processing States
This LSI has five processing states: the reset state, exception-handling state, bus-released state,
program execution state, and power-down state.
Reset State: In this state the CPU is reset. The power-on reset state is entered when the RESET
pin goes low. The manual reset state is entered when the RESET pin is high and the MRESET pin
is low. For more information on resets, see section 8, Exceptions.
In the power-on reset state, the internal state of the CPU and the on-chip peripheral module
registers are initialized. In the manual reset state, the internal state of the CPU and registers of on-
chip peripheral modules other than the BSC are initialized. Since the BSC is not initialized in the
manual reset state, refreshing operations continue. For details, see register descriptions for each
section.
Exception-Handling State: This is a transient state during which the CPU's processing state flow
is altered by a reset, general exception, or interrupt exception handling source.
In the case of a reset, the CPU branches to address H'A000 0000 and starts executing the user-
coded exception handling program.
In the case of a general exception or interrupt, the PC is saved in the SPC, the SR is saved in the
SSR, and the R15 is saved in SGR. The CPU branches to the start address of the user-coded
exception handling routine found from the sum of the contents of the vector base address and the
vector offset. See section 8, Exceptions, for more information on resets, general exceptions, and
interrupts.
Program Execution State: In this state, the CPU executes program instructions in sequence.
Rev. 1.0, 02/03, page 38 of 1294