SH7760 Datasheet, PDF (858/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
15 to 0 UMSR1[15:0]
Initial Value R/W
All 0
R/W
Description
Indicate that an unread received message has
been overwritten for Mailboxes 31 to 16.
0: Clearing condition: Write a 1 to this bit.
1: Unread received message is overwritten by
a new message or overrun condition.
Setting condition: A new message is
received before CANRXPR or CANRFPR is
cleared.
• CANUMSR0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0
_15 _14 _13 _12 _11 _10
_9
_8
_7
_6
_5
_4
_3
_2
_1
_0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 0 UMSR0[15:0]
Initial Value R/W
All 0
R/W
Description
Indicate that an unread received message has
been overwritten for Mailboxes 15 to 0.
0: Clearing condition: Write a 1 to this bit.
1: Unread received message is overwritten by
a new message or overrun condition.
Setting condition: A new message is
received before CANRXPR or CANRFPR is
cleared.
22.5.15 Timer Counter Register (CANTCNTR)
CANTCNTR is a 16-bit read/write register that allows the CPU to monitor and modify the value
of the Free Running Timer Counter. When the Timer rolls over or meets CANTCMR and TCR11
is set to 1, CANTCNTR is set to 0 and starts running again.
• CANTCNTR
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Rev. 1.0, 02/03, page 808 of 1294