SH7760 Datasheet, PDF (1028/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

27.3.4 MFI Memory Control Register (MFIMCR)
The MFIMCR is a 32-bit register that the external device uses to control the MFRAM via the
MFI.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
- LOCK - WT*³ - RD*³ -
- AI/AD
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W*¹ R R/W*¹ R R/W*¹ R
R R/W*¹
Bit
31 to 8
7
6
5
Bit
Name

LOCK

WT*³
Initial
Value
All 0
0
0
0
R/W
R
R/W*¹
R
R/W*¹
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Lock
This bit is used to lock read/write operations during
continuous access. Writing 1 to the LOCK bit retains the
values of the RD and WT bits simultaneously set until
clearing the LOCK bit to 0. Setting both the RD and
LOCK bits simultaneously to 1 puts the MFI in the
continuous read mode; setting both the WT and LOCK
bits simultaneously to 1 results in the continuous write
mode. Do not set the RD and WT bits simultaneously to
1.
Reserved
This bit is always read as 0. The write value should
always be 0.
Write
Setting this bit to 1 writes the MFIDATA value to the
MFRAM address indicated by MFIADR.*²
• Setting both the WT and LOCK bits simultaneously to
1 results in the continuous write mode and enables
high-speed data transfer *⁴. The WT value remains 1
until the WT bit is next written to 0, or until the LOCK
bit is cleared to 0.
• If not setting the LOCK bit simultaneously to 1, writing
to MFRAM is performed only once. The WT bit is
automatically cleared to 0.
Rev. 1.0, 02/03, page 978 of 1294