SH7760 Datasheet, PDF (763/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(2) Reception using Interrupt Data Flow Control
Start
Release reset,
specify configuration bits
in SSICR
Enable SSI module,
enable data interrupt,
enable error interrupts
Specify TRMD, EN, SCKD,
SWSD, MUEN, DEL, PDTA,
SDTA, SPDP, SWSP, SCKP,
SWL, DWL, CHNL
EN = 1,
DIEN = 1,
UIEN = 1, OIEN = 1
Wait for interrupt
from SSI
SSI
Yes
Error interrupt?
No
Read data from
receive data register
Use SSI status register bits
to realign data
after underflow/overflow
Yes
More data to be
received?
No
Disable SSI module,
disable data interrupt,
disable error interrupt,
enable idle interrupt
EN = 0,
DIEN = 0
UIEN = 0, OIEN = 0,
IIEN = 1
Wait for idle interrupt
from SSI module
End
Figure 20.24 Reception using Interrupt Data Flow Control
Rev. 1.0, 02/03, page 713 of 1294