SH7760 Datasheet, PDF (683/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

18.5.4 Transmit End Interrupt
If the TEIE bit is always set to 1 during continuous transmission, unnecessary transmit end
interrupts (SIMTEI) occur because the TEND bit is set to 1 every time transmission is completed.
To avoid unnecessary SIMTEI requests, the TEIE bit in SISCR should be set to 1 only after the
last transmit data is written to SITDR and SITSR starts transmission.
Figure 18.10 shows the signal waveforms when TEIE is set to 1.
Transfer frame
Transfer frame
Last frame
(DE)
(DE)
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 DP Ds D0 D1 D2 D3 D4 D5 D6 D7 DP Ds D0 D1 D2 D3 D4 D5 D6 D7 DP
TDRE
TEND
TEIE
Unnecessary TEND set timing
SIMTEI
request
Figure 18.10 TEIE Set Timing
TEIE set timing
18.5.5 Standby Mode Switching
When switching between the smart card interface mode and standby mode, in order to maintain
the clock duty, the following switching procedure should be used. Figure 18.11 shows standby
mode switching procedure. (1) to (7) in figure 18.11 correspond to items 1 to 7 described below.
• When changing from smart card interface mode to standby mode:
1. Write 0 to the TE and RE bits in SISCR, to stop transmission and reception operations. At the
same time, set the CKE1 bit to the value for the output-fixed state in standby mode.
2. Write 0 to the CKE0 bit in SISCR to stop the clock.
3. Wait for one clock cycle of the serial clock. During this interval, the duty is maintained, and
the clock output is fixed at the specified level.
4. Make the transition to standby mode.
Rev. 1.0,02/03, page 633 of 1294