SH7760 Datasheet, PDF (842/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
8
IRR8
0
R/W Mailbox Empty Interrupt Flag
Indicates that message transmission or
transmission cancellation has been successfully
ended, and the Mailbox is now ready to accept a
new message data for the next transmission. This
bit is set when at least one CANTXPR bit is
cleared. This bit is set by an OR'ed signal of the
CANTXACK and CANABACK bits, therefore, this
bit is automatically cleared when all the
CANTXACK and CANABACK bits are cleared.
Writing a 0 has no effect. Note that this bit does
not indicate that all CANTXPR bits are reset,
whereas GSR2 does.
0: Messages set for transmission or transmission
cancellation is not in progress.
Clearing condition: All the CANTXACK and
CANABACK bits are cleared.
1: Message has been transmitted or aborted, and
a new message can be stored.
Setting condition: One of the CANTXPR bits is
cleared by completion of transmission or
completion of transmission abort (i.e. in case
of CANMBIMR = 0, the CANTXACK or
CANABACK bit is set).
7
IRR7
0
R/W Overload Frame
Indicates that the HCAN2 has transmitted an
overload frame. It remains latched until reset by
writing a 1 to this bit position. Writing a 0 has no
effect.
0: Clearing condition: Write a 1 to this bit.
1: Setting condition: Overload frame is
transmitted.
Rev. 1.0, 02/03, page 792 of 1294