SH7760 Datasheet, PDF (933/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

25.3 Register Descriptions
This section describes the HAC registers. For details of register addresses and register statuses in
each processing, see section 32, List of Registers. Since these registers function in the same way in
both channels 0 and 1, they are not discriminated by channel number in the description below.
Table 25.2 Register Configuration (1)
Ch. Register Name
Abbrev. R/W
0 Control and status register 0
HACCR0 R/W
Command/status address register 0 HACCSAR0 R/W
Command/status data register 0
HACCSDR0 R/W
PCM left channel register 0
HACPCML0 R/W
PCM right channel register 0
HACPCMR0 R/W
TX interrupt enable register 0
HACTIER0 R/W
TX status register 0
HACTSR0 R/W
RX interrupt enable register 0
HACRIER0 R/W
RX status register 0
HACRSR0 R/W
HAC control register 0
HACACR0 R/W
1 Control and status register 1
HACCR1 R/W
Command/status address register 1 HACCSAR1 R/W
Command/status data register 1
HACCSDR1 R/W
PCM left channel register 1
HACPCML1 R/W
PCM right channel register 1
HACPCMR1 R/W
TX interrupt enable register 1
HACTIER1 R/W
TX status register 1
HACTSR1 R/W
RX interrupt enable register 1
HACRIER1 R/W
RX status register 1
HACRSR1 R/W
HAC control register 1
HACACR1 R/W
P4
Address
Area 7
Address
Sync
Size Clock
H’FE24 0008 H’1E24 0008 32 Pck
H’FE24 0020 H’1E24 0020 32 Pck
H’FE24 0024 H’1E24 0024 32 Pck
H’FE24 0028 H’1E24 0028 32 Pck
H’FE24 002C H’1E24 002C 32 Pck
H’FE24 0050 H’1E24 0050 32 Pck
H’FE24 0054 H’1E24 0054 32 Pck
H’FE24 0058 H’1E24 0058 32 Pck
H’FE24 005C H’1E24 005C 32 Pck
H’FE24 0060 H’1E24 0060 32 Pck
H’FE25 0008 H’1E25 0008 32 Pck
H’FE25 0020 H’1E25 0020 32 Pck
H’FE25 0024 H’1E25 0024 32 Pck
H’FE25 0028 H’1E25 0028 32 Pck
H’FE25 002C H’1E25 002C 32 Pck
H’FE25 0050 H’1E25 0050 32 Pck
H’FE25 0054 H’1E25 0054 32 Pck
H’FE25 0058 H’1E25 0058 32 Pck
H’FE25 005C H’1E25 005C 32 Pck
H’FE25 0060 H’1E25 0060 32 Pck
Rev. 1.0, 02/03, page 883 of 1294