SH7760 Datasheet, PDF (986/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

• INTSTR2
Bit: 7
-
Initial value: 0
R/W: R
6
5
-
-
0
0
RR
4
3
-
-
0
0
RR
2
1
0
-
FRDY
_TU
FRDYI
0
-
0
R R R/W
Bit
7 to 2
Bit
Name

Initial
Value
All 0
1
FRDY 
_TU
0
FRDYI 0
R/W Description
Interrupt
outputs
R
Reserved

These bits are always read as 0. The
write value should always be 0.
R
FIFO Ready Flag

Regardless of set values of DMAEN and
FRDYIE, this bit is read as 0 when FIFO
data amount matches the condition set in
DMACR[2:0], and otherwise, read as 1.
R/W FIFO Ready Interrupt
MMCI3
0: No interrupt
[Clearing condition]
Write 0 after reading FRDYI = 1.
1: Interrupt requested
[Setting condition]
When remained FIFO data does not
match the assert condition set in DMACR
while DMAEN = 1 and FRDYIE = 1.
Note: FRDYI will be set on the setting
condition after clearing. To clear it,
disable the flag setting by FRDYIE
in INTCR2.
Rev. 1.0, 02/03, page 936 of 1294