SH7760 Datasheet, PDF (411/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Section 11 Direct Memory Access Controller (DMAC)
This LSI includes an on-chip eight-channel direct memory access controller (DMAC). The DMAC
can be used in place of the CPU to perform high-speed data transfers among external devices
equipped with DACK (DMA transfer end notification), external memories, memory-mapped
external devices, and on-chip peripheral modules. Using the DMAC reduces the burden on the
CPU and increases the operating efficiency of this LSI.
11.1 Features
The DMAC has the following features.
• Number of channels: Eight channels
• Address space: Physical address space
• Selection of data length: 8-bit, 16-bit, 32-bit, 64-bit, or 32-byte transfer data length
• Maximum number of transfers: 16 M (16,777,216) transfers
• Selection of DMA mode: External request 2-channel mode or DMABRG mode
• Selection of address mode: Single address mode*¹ or dual address mode
• Selection of transfer requests: External request*², requests from on-chip peripheral modules*³,
or auto-request
• Selection of bus mode: Cycle steal mode or burst mode
• Selection of priority order: Fixed priority mode or round robin mode
• Channel functions: Different transfer modes (address mode, bus mode, and transfer requests)
can be set for each channel.
• Interrupt request: Interrupt request can be sent to the CPU on completion of data transfer.
Notes: *1. In DMABRG mode, only synchronous DRAM can be specified.
*2. External request 2-channel mode: DREQ0 (corresponds to channel 0) and DREQ1
(corresponds to channel 1)
DMABRG mode: DREQ0 to DREQ3 (can be set for all channels)
*3.External request 2-channel mode: Transfer requests cannot be accepted from the LCDC,
HAC, SSI, and USB.
DMABRG mode: Transfer requests can be accepted from all on-chip peripheral
modules with the DMA transfer request function. (Note that transfer requests from the
LCDC, HAC, SSI, and USB can only be accepted in channel 0.)
Rev. 1.0, 02/03, page 361 of 1294