SH7760 Datasheet, PDF (454/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
1
START
0
R/W DMA Transfer Start
Setting this bit to 1 starts a USB DMA transfer.
When the USB DMA transfer is completed, this bit
is automatically cleared to 0.
• When writing
0: Invalid
1: Starts a USB DMA transfer
• When reading
0: USB DMA transfer is stopped
1: USB DMA transfer is being performed
0

0
R
Reserved
This bit is always read as 0. The write value
should always be 0.
11.4 Operation
When a DMA transfer request is issued, the DMAC starts the transfer according to the
predetermined channel priority order. It ends the transfer when the transfer end conditions are
satisfied. Transfers can be requested in three modes: auto-request, external request, and on-chip
peripheral module request. There are two modes for DMA transfer: single address mode and dual
address mode. Either burst mode or cycle steal mode can be selected as the bus mode.
11.4.1 DMA Transfer Procedure
After the desired transfer conditions have been set in SAR, DAR, DMATCR, CHCR, DMAOR,
DMARCR, DMARSRA, and DMARSRB, the DMAC transfers data according to the following
procedure:
1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0).
2. When a transfer request is issued and transfer has been enabled, the DMAC transfers one
transfer unit of data (determined by bits TS2 to TS0). In auto-request mode, the transfer begins
automatically when the DE and DME bits are set to 1. The DMATCR value is decremented by
1 for each transfer. The actual transfer flow depends on the address mode and bus mode.
3. When the specified number of transfers have been completed (when the DMATCR value
reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, the DMAC
sends a DMTE interrupt request to the CPU.
4. If a DMAC address error or NMI interrupt occurs, the DMAC suspends the transfer. It also
suspends the transfer when the DE bit in CHCR or the DME bit in DMAOR is cleared to 0. In
the event of an address error, the DMAC issues a forced DMAE interrupt request to the CPU.
For details of DMA transfer end and suspension, see section 11.4.6, Ending DMA Transfer.
Rev. 1.0, 02/03, page 404 of 1294