SH7760 Datasheet, PDF (534/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
5
RSTS
0
R/W Reset Select
Specifies the kind of reset to be performed when
WTCNT overflows in watchdog timer mode. This
setting is ignored in interval timer mode.
0: Power-on reset
1: Manual reset
4
WOVF
0
R/W Watchdog Timer Overflow Flag
Indicates that WTCNT has overflowed in watchdog
timer mode. This flag is not set in interval timer
mode.
0: No overflow
1: WTCNT has overflowed in watchdog timer mode
3
IOVF
0
R/W Interval Timer Overflow Flag
Indicates that WTCNT has overflowed in interval
timer mode. This flag is not set in watchdog timer
mode.
0: No overflow
1: WTCNT has overflowed in interval timer mode
2
CKS2
0
1
CKS1
0
0
CKS0
0
R/W Clock Select 2 to 0
R/W These bits select the clock used for the WTCNT
R/W count from eight clocks obtained by dividing the
input clock of Frequency divider 1×1 clock. When
PLL1 is switched on or off, the clock after the
switching is used. The overflow cycles shown below
are for use of a 33-MHz input clock and PLL circuit
1 on (×6).
Clock Division Ratio Overflow Cycle
000: 1/32
001: 1/64
010: 1/128
011: 1/256
100: 1/512
101: 1/1024
110: 1/2048
111: 1/4096
41 µs
82 µs
164 µs
328 µs
656 µs
1.31 ms
2.62 ms
5.25 ms
Up counting may not be performed correctly if bits
CKS2 to CKS0 are modified while the WDT is
running. Always stop the WDT before modifying
these bits.
Rev. 1.0, 02/03, page 484 of 1294