SH7760 Datasheet, PDF (740/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

20.3.2 Status Register (SSISR)
SSISR is configured by status flags that indicate the operating status of the SSI module and bits
that indicate the current channel number and word number.
Bit: 31 30
-
-
Initial value: -
-
R/W: R R
Bit: 15 14
-
-
Initial value: -
-
R/W: R R
Bit
Bit Name
31 to 29 
28
DMRQ
29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
DMRQ UIRQ OIRQ IIRQ DIRQ
-
-
-
-
-
-
-
-
-
0
0
0
1
0
-
-
-
-
-
-
-
-
R R R/W* R/W* R R R
R
R
R
R RR
R
13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
CHNO1 CHNO0 SWNO IDST
-
-
-
-
-
-
-
-
-
-
0
0
1
1
RRR
RRRR
R
R
R
R RR
R
Initial Value R/W Description

R
Reserved
These bits are always read as an undefined
value. The write value should always be 0.
0
R
DMA Request Status Flag
This status flag allows the CPU to see the status
of the DMA request of SSI module.
TRMD = 0 (Receive Mode):
• If DMRQ = 1 then SSIRDR has unread data.
• If SSIRDR is read then DMRQ = 0 until there
is new unread data.
TRMD = 1 (Transmit Mode):
• If DMRQ = 1, SSITDR requests data to be
written to continue the transmission onto the
audio serial bus.
• Once data is written to SSITDR then DMRQ =
0 until further transmit data is requested.
Rev. 1.0, 02/03, page 690 of 1294