SH7760 Datasheet, PDF (669/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

18.3.10 Serial Control 2 Register (SISC2R)
SISC2R is an 8-bit readable/writable register that enables or disables receive data full interrupt
(SIMRXI) requests.
Bit: 7
6
5
4
3
2
1
0
EIO -
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R
R
R
R
R
R
R
Bit
Bit
Name
7
EIO
6 to 0 
Initial
Value
0
All 0
R/W Description
R/W Error Interrupt Only
When the EIO bit is 1, even if the RIE bit is set to 1, a
receive data full interrupt (SIMRXI) request is not sent to
the CPU. When the DMAC is used with this setting, the
CPU processes only SIMERI requests.
Receive data full interrupt (SIMRXI) requests are enabled
or disabled by the RIE bit setting.
R
Reserved
These bits are always read as 0. The write value should
also always be 0.
18.3.11 Guard Extension Register (SIGRD)
SIGRD is an 8-bit readable/writable register that sets the time added for guardtime.
Bit:
Initial value:
R/W:
7
SIG
RD7
0
R/W
6
SIG
RD6
0
R/W
5
SIG
RD5
0
R/W
4
SIG
RD4
0
R/W
3
SIG
RD3
0
R/W
2
SIG
RD2
0
R/W
1
SIG
RD1
0
R/W
0
SIG
RD0
0
R/W
Rev. 1.0,02/03, page 619 of 1294