SH7760 Datasheet, PDF (1157/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

value saved to SPC is the address of the branch destination (when the branch is made) or the
instruction following the delay slot instruction (when the branch is not made).
4. When operand access (address only) is set as a break condition, the address of the instruction
to be executed after the instruction at which the condition match occurred is saved to SPC.
5. When operand access (address + data) is set as a break condition, execution of the instruction
at which the condition match occurred is completed. A user break interrupt is generated before
execution of instructions from one instruction later to four instructions later. It is not possible
to specify at which instruction, from one later to four later, the interrupt will be generated. The
start address of the instruction after the instruction for which execution is completed at the
point at which user break interrupt handling is started is saved to SPC. If an instruction
between one instruction later and four instructions later causes another exception, control is
performed as follows. Designating the exception caused by the break as exception 1, and the
exception caused by an instruction between one instruction later and four instructions later as
exception 2, memory updates and register updates that can not be performed by exception 2 are
guaranteed irrespective of the existence of exception 1. The PC value saved is the address of
the first instruction for which execution is suppressed. Whether exception 1 or exception 2 is
used for the exception jump destination and the value written to the exception register
(EXPEVT/INTEVT) is not guaranteed. However, if exception 2 is from a source which is not
synchronized with an instruction (external interrupt or peripheral module interrupt), exception
1 is used for the exception jump destination and the value written to the exception register
(EXPEVT/INTEVT).
31.3.8 Contiguous A and B Settings for Sequential Conditions
When channel A match and channel B match timings are close together, a sequential break may
not be guaranteed. Rules relating to the guaranteed range are given below.
1. Instruction access matches on both channel A and channel B
Instruction B is 0 instructions after
instruction A
Equivalent to setting the same address. This setting is
prohibited.
Instruction B is 1 instruction after
instruction A
Sequential operation is not guaranteed.
Instruction B is 2 or more instructions Sequential operation is guaranteed.
after instruction A
2. Instruction access match on channel A, operand access match on channel B
Instruction B is 0 or 1 instruction after Sequential operation is not guaranteed.
instruction A
Instruction B is 2 or more instructions Sequential operation is guaranteed.
after instruction A
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