SH7760 Datasheet, PDF (14/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

11.6.7 Forced Termination of DMA Audio Transfer...................................................... 453
11.6.8 Double Buffer Control for Audio Data ................................................................ 456
11.6.9 HAC/SSI Endian Conversion Function ............................................................... 456
11.6.10 Switching Data for Left and Right Channels ....................................................... 457
11.6.11 LCDC DMA Transfer .......................................................................................... 458
11.6.12 USB DMA Transfer............................................................................................. 458
11.6.13 USB Endian Conversion Function....................................................................... 460
11.6.14 DMABRG Interrupts ........................................................................................... 462
11.7 Usage Notes ...................................................................................................................... 464
Section 12 Clock Pulse Generator (CPG) .........................................................465
12.1 Features............................................................................................................................. 465
12.2 Input/Output Pins .............................................................................................................. 468
12.3 Clock Operating Modes .................................................................................................... 469
12.4 Register Descriptions ........................................................................................................ 471
12.4.1 Frequency Control Register (FRQCR) ................................................................ 472
12.4.2 Clock Division Register (DCKDR) ..................................................................... 474
12.4.3 Module Clock Control Register (MCKCR) ......................................................... 475
12.5 Frequency Changing Method............................................................................................ 476
12.5.1 Switching between PLL Circuit 1 On/Off (When PLL Circuit 2 is Off) ............. 476
12.5.2 Switching between PLL Circuit 1 On/Off (When PLL Circuit 2 is On).............. 476
12.5.3 Changing Bus Clock Frequency Division Ratio (When PLL Circuit 2 is On)..... 477
12.5.4 Changing Bus Clock Frequency Division Ratio (When PLL Circuit 2 is Off).... 477
12.5.5 Changing Frequency Division Ratio of CPU Clock or Peripheral Clock ............ 477
12.5.6 Switching between PLL Circuit 3 On/Off ........................................................... 477
12.5.7 Changing DCK Output Clock Division Ratio...................................................... 478
12.5.8 Controlling DCK Output Clock ........................................................................... 478
12.5.9 Controlling CKIO Output Clock.......................................................................... 479
12.6 Usage Notes ...................................................................................................................... 479
Section 13 Watchdog Timer (WDT) .................................................................481
13.1 Features............................................................................................................................. 481
13.2 Register Descriptions ........................................................................................................ 482
13.2.1 Watchdog Timer Counter (WTCNT)................................................................... 483
13.2.2 Watchdog Timer Control/Status Register (WTCSR)........................................... 483
13.2.3 Notes on Register Access..................................................................................... 485
13.3 Operation .......................................................................................................................... 486
13.3.1 Standby Clearing Procedure ................................................................................ 486
13.3.2 Frequency Changing Procedure ........................................................................... 486
13.3.3 Using Watchdog Timer Mode.............................................................................. 487
13.3.4 Using Interval Timer Mode ................................................................................. 487
Rev. 1.0, 02/03, page xii of xlviii