SH7760 Datasheet, PDF (1073/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

29.4.2 Multi Mode
In multi mode, analog inputs for the specified channels (one or more) are converted once each as
shown below.
1. When the ADST bit in ADCSR is set to 1 by software or an external trigger input, A/D
conversion starts with the first channel (AN0).
2. When multiple channels are selected, the input signal for the second channel is converted after
the A/D conversion for the first channel ends.
3. When conversion of each channel ends, the conversion results are transmitted to the A/D
conversion data register that corresponds to the channel.
4. When conversion of all selected channel ends, the ADF bit of ADCSR is set to 1. If the ADIE
bit is also set to 1, an ADI interrupt is requested at this time.
5. When A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter
becomes idle. When the ADST bit is cleared to 0 during A/D conversion, the conversion is
halted and the A/D converter becomes idle.
Writing 0 to the ADF bit after reading ADF = 1 clears the ADF bit.
Typical operations when three channels (AN0 to AN2) are selected in multi mode are described
below. Figure 29.3 shows a timing diagram for this example.
1. Select multi mode as the operating mode (MDS1 = 1 and MDS0 = 0) and AN0 to AN2 as the
analog input channels (CH1 = 1 and CH0 = 0). Then start A/D conversion (ADST = 1).
2. A/D conversion of the first channel (AN0) starts. When the conversion ends, the result is
transferred into ADDRA. Next, the second channel (AN1) is selected automatically and A/D
conversion starts.
3. Conversion proceeds in the same way up to the third channel (AN2).
4. When conversion of all selected channels (AN0 to AN2) ends, the ADF bit is set to 1 and the
ADST bit is cleared to 0 to stop A/D conversion.
If the DMASL bit is cleared to 0 and the ADIE bit is set to 1 at this time, an ADI interrupt is
generated after A/D conversion ends.
Rev. 1.0, 02/03, page 1023 of 1294